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DP7401 ? nidec copal electronics corp. 1 h . v e r 2 1 0 2 - d m . o n . c o d characteristics subject to change without notice quad digital potentiometers (dp) with 64 taps and spi interface features four linear taper digital potentiometers 64 resistor taps per potentiometer end to end resistance 2.5k ? , 10k ? , 50k ? or 100k ? potentiometer control and memory access via spi interface: mode (0, 0) and (1, 1) low wiper resistance, typically 80 ? nonvolatile memory storage for up to four wiper settings for each potentiometer automatic recall of saved wiper settings at power up 2.5 to 6.0 volt operation standby current less than 1a 1,000,000 nonvolatile write cycles 100 year nonvolatile memory data retention 24-lead soic and 24-lead tssop industrial temperature range for ordering information details, see page 14. pin configuration description the DP7401 is four digital potentiometers (dps) integrated with control logic and 16 bytes of nvram memory. each dp consists of a series of 63 resistive elements connected between two externally accessible end points. the tap points between each resistive element are connected to the wiper outputs with cmos switches. a separate 6-bit control register (wcr) independently controls the wiper tap switches for each dp. associated with each wiper control register are four 6-bit non-volatile memory data registers (dr) used for storing up to four wiper settings. writing to the wiper control register or any of the non-volatile data registers is via a spi serial bus. on power-up, the contents of the first data register (dr0) for each of the four potentiometers is automatically loaded into its respective wiper control register. the DP7401 can be used as a potentiometer or as a two terminal, variable resistor. it is intended for circuit level or system level adjustments in a wide variety of applications. functional diagram 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 dp 7401 v cc r l0 r h0 r w0 cs wp si a 1 r l1 r h1 r w1 gnd nc r l3 r h3 r w3 a 0 so hold sck r l2 r h2 r w2 nc 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 dp 7401 si a 1 r l1 r h1 r w1 gnd nc r w2 r h2 r l2 sck hold wp cs r w 0 r h0 r l0 v cc nc r l3 r h3 r w 3 a 0 so soic package (w) tss o p package (y) nonvolatile data registers control logic wiper control registers spi bus interface r w0 r w1 r w2 r w3 r l0 a 0 a 1 cs sck si so r l1 r l2 r l3 r h0 r h1 r h2 r h3 wp
DP7401 doc. no. md-2012 rev. h 2 ? nidec copal electronics corp. characteristics subject to change without notice pin descriptions si: serial input si is the serial data input pin. this pin is used to input all opcodes, byte addresses and data to be written to the DP7401. input data is latched on the rising edge of the serial clock. so: serial output so is the serial data output pin. this pin is used to transfer data out of the DP7401. during a read cycle, data is shifted out on the falling edge of the serial clock. sck: serial clock sck is the serial clock pin. this pin is used to synchronize the communication between the microcontroller and the DP7401. opcodes, byte addresses or data present on the si pin are latched on the rising edge of the sck. data on the so pin is updated on the falling edge of the sck. a0, a1: device address inputs these inputs set the device address when addressing multiple devices. a total of four devices can be addressed on a single bus. a match in the slave address must be made with the address input in order to initiate communication with the DP7401. r h , r l : resistor end points the four sets of r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. r w : wiper the four r w pins are equivalent to the wiper terminal of a mechanical potentiometer. cs : chip select cs is the chip select pin. cs low enables the DP7401 and cs high disables the DP7401. cs high takes the so output pin to high impedance and forces the devices into a standby mode (unless an internal write operation is underway). the DP7401 draws zero current in the standby mode. a high to low transition on cs is required prior to any sequence being initiated. a low to high transition on cs after a valid write sequence is what initiates an internal write cycle. wp : write protect wp is the write protect pin. the write protect pin will allow normal read/write operations when held high. when wp is tied low, all non-volatile write operations to the data reg isters are inhibited (change of wiper control register is allowed). wp going low while cs is still low will interrupt a write to the registers. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation. hold : hold the hold pin is used to pause transmission to the DP7401 while in the middle of a serial sequence without having to retransmit entire sequence at a later time. to pause, hold must be brought low while sck is low. the so pin is in a high impedance state during the time the part is paused, and transitions on the si pins will be ignored. to resume communication, hold is brought high, while sck is low. (hold should be held high any time this function is not being used.) hold may be tied high directly to v cc or tied to v cc through a resistor. pin# (soic) pin# (tssop) name function 119v cc supply voltage 220r l0 low reference terminal for potentiometer 0 321r h0 high reference terminal for potentiometer 0 422r w0 wiper terminal for potentiometer 0 523 cs chip select 624 wp write protection 71si serial input 82a1 device address 93r l1 low reference terminal for potentiometer 1 10 4 r h1 high reference terminal for potentiometer 1 11 5 r w1 wiper terminal for potentiometer 1 12 6 gnd ground 13 7 nc no connect 14 8 r w2 wiper terminal for potentiometer 2 15 9 r h2 high reference terminal for potentiometer 2 16 10 r l2 low reference terminal for potentiometer 2 17 11 sck bus serial clock 18 12 hold hold 19 13 so serial data output 20 14 a0 device address, lsb 21 15 r w3 wiper terminal for potentiometer 3 22 16 r h3 high reference terminal for potentiometer 3 23 17 r l3 low reference terminal for potentiometer 3 24 18 nc no connect
DP7401 ? nidec copal electronics corp. 3 doc. no. md-2012 rev. h characteristics subject to change without notice serial bus protocol the dp7041 supports the spi bus data transmission protocol. the synchronous serial peripheral interface (spi) helps the DP7401 to interface directly with many of today's popular microcontrollers. the dp7041 contains an 8-bit instruction register. the instruction set and the operation codes are detailed in the instruction set table 3. after the device is selected with cs going low the first byte will be received. the part is accessed via the si pin, with data being clocked in on the rising edge of sck. the first byte contains one of the six op-codes that define the operation to be performed. device operation the DP7401 is four resistor arrays integrated with spi serial interface logic, four 6-bit wiper control registers and sixteen 6-bit, non-volatile memory data registers. each resistor array contains 63 separate resistive elements connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l ). r h and r l are symmetrical and may be interchanged. the tap positions between and at the ends of the series resistors are connected to the output wiper terminals (r w ) by a cmos transistor switch. only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. data can be read or written to the wiper control registers or the non- volatile memory data registers via the spi bus. additional instructions allows data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. also, the device can be instructed to operate in an "increment/decrement" mode.
DP7401 doc. no. md-2012 rev. h 4 ? nidec copal electronics corp. characteristics subject to change without notice absolute maximum ratings (1) parameters ratings units c o 5 2 1 + o t 5 5 - s a i b r e d n u e r u t a r e p m e t c 0 5 1 + o t 5 6 - e r u t a r e p m e t e g a r o t s voltage on any pin with respect to v ss (1) (2) v + o t 0 . 2 - cc + 2.0 v v cc v 0 . 7 + o t 2 . 0 - d n u o r g o t t c e p s e r h t i w package power dissipation capability (t a w 0 . 1 ) c o 5 2 = c o 0 0 3 ) s 0 1 ( e r u t a r e p m e t g n i r e d l o s d a e l wiper current 12 ma recommended operating conditions parameters ratings units v cc +2.5 to +6 v c 5 8 + o t 0 4 - e r u t a r e p m e t l a i r t s u d n i potentiometer characteristics over recommended operatin g conditions unless otherwise stated. symbol parameter test conditions min typ max units r pot k 0 0 1 ) 0 0 - ( e c n a t s i s e r r e t e m o i t n e t o p ? r pot k 0 5 ) 0 5 - ( e c n a t s i s e r r e t e m o i t n e t o p ? r pot k 0 1 ) 0 1 - ( e c n a t s i s e r r e t e m o i t n e t o p ? r pot k 5 . 2 ) 5 . 2 - ( e c n a t s i s e r r e t e m o i t n e t o p ? potentiometer resistance tolerance % 0 2 r pot % 1 g n i h c t a m power rating 25c, each pot 50 mw i w a m 6 t n e r r u c r e p i w r w wiper resistance i w =3ma @v cc = 3v 300 ? r w wiper resistance i w =3ma @v cc = 5v 80 150 ? v term voltage on any r h or r l pin v ss v d n g v 0 = cc v ) 4 ( e s i o n n v nv hz % 6 . 1 n o i t u l o s e r absolute linearity (5) r w (n)(actual) - r(n)(expected) (8) 1 lsb (7) relative linearity (6) r w (n+1) - [r w (n) + lsb] (8) 0.2 lsb (7) tc rpot temperature coefficient of r pot c o / m p p 0 0 3 ) 4 ( tc ratio c o / m p p 0 2 ) 4 ( t n e i c i f f e o c . p m e t c i r t e m o i t a r c h /c l /c w f p 5 2 / 0 1 / 0 1 ) 4 ( s e c n a t i c a p a c r e t e m o i t n e t o p fc frequency response r pot =50k ? 0.4 mhz notes: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliabi lity. (2) the minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C2.0v for periods of less than 20ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20ns. (3) latch-up protection is provided for stresses up to 100ma on address and data pins from C1v to v cc +1v. (4) this parameter is tested initially and after a design or process change that affects the parameter. (5) absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when use d as a potentiometer. (6) relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentio- meter. it is a measure of the error in step size. (7) lsb = r tot / 63 or (r h - r l ) / 63, single pot (8) n = 0, 1, 2, ..., 63 ) 4 ( tbd (4)
DP7401 ? nidec copal electronics corp. 5 h . v e r 2 1 0 2 - d m . o n . c o d characteristics subject to change without notice d.c. operating characteristics over recommended operatin g conditions unless otherwise stated. s t i n u x a m n i m s n o i t i d n o c t s e t r e t e m a r a p l o b m y s i cc power supply current f scl = 2mhz, so = open inputs = gnd 1ma i sb standby current (v cc = 5.0v) v in =gndorv cc , so = open 1 a i li input leakage current v in = gnd to v cc 10 a i lo output leakage current v out = gnd to v cc 10 a v il v 1 - e g a t l o v w o l t u p n i cc x 0.3 v v ih v e g a t l o v h g i h t u p n i cc x 0.7 v cc + 1.0 v v ol1 output low voltage (v cc = 3.0v) i ol v 4 . 0 a m 3 = pin capacitance (1) available over recommended operating range from t a = 25oc, f = 1.0mhz, v cc = 5v (unless otherwise noted). s t i n u . x a m s n o i t i d n o c t s e t l o b m y s c out v ) o s ( e c n a t i c a p a c t u p t u o out =0v 8 pf c in input capacitance ( cs, sck, si, wp, hold) v in =0v 6 pf a.c. characteristics over recommended operatin g conditions unless otherwise stated. s t i n u x a m p y t n i m s n o i t i d n o c t s e t r e t e m a r a p l o b m y s t su s n 0 5 e m i t p u t e s a t a d t h s n 0 5 e m i t d l o h a t a d t wh s n 5 2 1 e m i t h g i h k c s t wl s n 5 2 1 e m i t w o l k c s f sck z h m 3 c d y c n e u q e r f k c o l c t lz hold to output low z 50 ns t ri ( 1) s 2 e m i t e s i r t u p n i t fi (1) s 2 e m i t l l a f t u p n i t hd hold setup time 100 ns t cd hold hold time 100 ns t wc s m 0 1 e m i t e l c y c e t i r w t v s n 0 5 2 w o l k c o l c m o r f d i l a v t u p t u o t ho s n 0 e m i t d l o h t u p t u o t dis s n 0 5 2 e m i t e l b a s i d t u p t u o t hz hold to output high z 100 ns t cs cs high time 250 ns t css cs setup time 250 ns t csh cs hold time c l =50pf 250 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter.
DP7401 doc. no. md-2012 rev. h 6 ? nidec copal electronics corp. characteristics subject to change without notice power up timing (1)(2) s t i n u x a m r e t e m a r a p l o b m y s t pur s m 1 n o i t a r e p o d a e r o t p u - r e w o p t puw s m 1 n o i t a r e p o e t i r w o t p u - r e w o p write cycle limits s t i n u x a m r e t e m a r a p l o b m y s t wr s m 5 e m i t e l c y c e t i r w reliability characteristics symbol parameter reference test method min max units n end (3) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (3) data retention mil-std-883, test method 1008 100 years v zap (3) esd susceptibility mil-std-883, test method 3015 2000 v i lth (3) a m 0 0 1 7 1 d r a d n a t s c e d e j p u - h c t a l figure 1. synchronous data timing figure 2. hold timing notes: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are delays required from the time v cc is stable until the specified operation can be initiated. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) dashed line = mode (1, 1) - - - - - - - valid in v ih v il t css v ih v il v il v ih v oh v ol hi-z t su t h t wh t wl t v t cs t csh t ho t dis hi-z cs sck si so t ri t fi cs sck hold so t cd t hd t hd t cd t lz t hz high impedance
DP7401 ? nidec copal electronics corp. 7 doc. no. md-2012 rev. h characteristics subject to change without notice instruction and register description device type / address byte the first byte sent to the DP7401 from the master/ processor is called the device address byte. the most significant four bits of the device type address are a device type identifier. these bits for the DP7401 are fixed at 0101[b] (refer to table 1). the two least significant bits in the slave address byte, a1 - a0, are the internal slave address and must match the physical device address which is defined by the state of the a1 - a0 input pins for the DP7401 to successfully continue the command sequence. only the device which slave address matches the incoming device address sent by the master executes the instruction. the a1 - a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss .the remaining two bits in the device address byte must be set to 0. instruction byte the next byte sent to the DP7401 contains the instruction and register pointer information. the four most significant bits used provide the instruction opcode i [3:0]. the r1 and r0 bits point to one of the four data registers of each associated potentiometer. the least two significant bits point to one of four wiper control registers. the format is shown in table 2. data register selection data register selected r1 r0 dr0 0 0 dr1 0 1 dr2 1 0 dr3 1 1 table 1. identification byte format table 2. instruction byte format id3 id2 id1 id0 0 0 a1 a0 0101 (msb) (lsb) device type identifier slave address i3 i2 i1 i0 r1 r0 p1 p0 ( msb ) ( lsb ) wcr/pot selection instruction opcode data register selection
DP7401 doc. no. md-2012 rev. h 8 ? nidec copal electronics corp. characteristics subject to change without notice wiper control and data registers wiper control register (wcr) the DP7401 contains four 6-bit wiper control registers, one for each potentiometer. the wiper control register output is decoded to select one of 64 switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written by the host via write wiper control register instruction; it may be written by transferring the contents of one of four associated data registers via the xfr data register instruction, it can be modified one step at a time by the increment/decrement instruction (see instruction section for more details). finally, it is loaded with the content of its data register zero (dr0) upon power-up. the wiper control register is a volatile register that loses its contents when the DP7401 is powered- down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. data registers (dr) each potentiometer has four 6-bit non-volatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper control register. any data changes in one of the data registers is a non-volatile operation and will take a maximum of 5ms. write in process the contents of the data registers are saved to nonvolatile memory when the cs input goes high after a write sequence is received. the status of the internal write cycle can be monitored by issuing a read status command to read the write in process (wip) bit. instructions four of the nine instructions are three bytes in length. these instructions are: read wiper control register C read the current wiper position of the selected potentiometer in the wcr write wiper control register C change current wiper position in the wcr of the selected potentiometer read data register C read the contents of the selected data register write data register C write a new value to the selected data register read status C read the status of the wip bit which when set to "1" signifies a write cycle is in progress. table 3. instruction set note: 1/0 = data is one or zero instruction set instruction i3 i2 i1 i0 r1 r0 wcr1/ p1 wcr0/ p0 operation read wiper control register 1 0 0 1 0 0 1/0 1/0 read the contents of the wiper control register pointed to by p1-p0 write wiper control register 1 0 1 0 0 0 1/0 1/0 write new value to the wiper control register pointed to by p1-p0 read data register 1 0 1 1 1/0 1/0 1/0 1/0 read the contents of the data register pointed to by p1-p0 and r1-r0 write data register 1 1 0 0 1/0 1/0 1/0 1/0 write new value to the data register pointed to by p1-p0 and r1-r0 xfr data register to wiper control register 1 1 0 1 1/0 1/0 1/0 1/0 transfer the contents of the data register pointed to by p1-p0 and r1-r0 to its associated wiper control register xfr wiper control register to data register 1 1 1 0 1/0 1/0 1/0 1/0 transfer the contents of the wiper control register pointed to by p1-p0 to the data register pointed to by r1-r0 global xfr data registers to wiper control registers 0 0 0 1 1/0 1/0 0 0 transfer the contents of the data registers pointed to by r1-r0 of all four pots to their respective wiper control registers global xfr wiper control registers to data register 1 0 0 0 1/0 1/0 0 0 transfer the contents of both wiper control registers to their respective data registers pointed to by r1-r0 of all four pots increment/decrement wiper control register 0 0 1 0 0 0 1/0 1/0 enable increment/decrement of the control latch pointed to by p1-p0 read status (wip bit) 0101 0 0 0 1 read wip bit to check internal write cycle status
DP7401 ? nidec copal electronics corp. 9 h . v e r 2 1 0 2 - d m . o n . c o d characteristics subject to change without notice the basic sequence of the three byte instructions is illustrated in figure 4. these three-byte instructions exchange data between the wcr and one of the data registers. the wcr controls the position of the wiper. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to non- volatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. four instructions require a two-byte sequence to complete, as illustrated in figure 3. these instructions transfer data between the host/processor and the DP7401; either between the host and one of the data registers or directly between the host and the wiper control register. these instructions are: xfr data register to wiper control register this transfers the contents of one specified data register to the associated wiper control register. xfr wiper control register to data register this transfers the contents of the specified wiper control register to the specified associated data register. gang xfr data register to wiper control register this transfers the contents of all specified data registers to the associated wiper control registers. gang xfr wiper counter register to data register this transfers the contents of all wiper control registers to the specified associated data registers. increment/decrement command the final command is increment/decrement (figure 5). the increment/decrement command is different from the other commands. once the command is issued the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. for each sck clock pulse (t high ) while si is high, the selected wiper will move one resistor segment towards the r h terminal. similarly, for each sck clock pulse while si is low, the selected wiper will move one resistor segment towards the r l terminal. see instructions format for more detail. figure 3. two-byte instruction sequence figure 4. three-byte instruction sequence figure 5. increment/decrement instruction sequence 0101 a2 a0 i2 i1 i0 r1 r0 p1 si id3 id2 id1 id0 p0 device id internal instruction opcode address register address pot/wcr address a1 a3 i3 00 i3 i2 i1 i0 r1 r0 id3 id2 id1 id0 device id internal instruction opcode address data register address pot/wcr address wcr[7:0] or data register d[7:0] 010100 a2 a1 a0 p1 p0 si d7 d6 d5 d4 d3 d2 d1 d0 a3 i3 i2 i1 i0 id3 id2 id1 id0 device id internal instruction opcode address data register address pot/wcr address 010100 a2 a1 a0 r0 p1 p0 si i n c 1 i n c 2 i n c n d e c 1 d e c n r1 a3
DP7401 doc. no. md-2012 rev. h 10 ? nidec copal electronics corp. characteristics subject to change without notice figure 6. increment/decrement timing limits instruction format read wiper control register (wcr) a t a d n o i t c u r t s n i s e s s e r d d a e c i v e d cs 0 1 0 1 0 0 a1 a0 1 0 0 1 0 0 p1 p0 7 0 6 0 543210 cs write wiper control register (wcr) a t a d n o i t c u r t s n i s e s s e r d d a e c i v e d cs 0 1 0 1 0 0 a1 a0 1 0 1 0 0 0 p1 p0 7 0 6 0 543210 cs read data register (dr) a t a d n o i t c u r t s n i s e s s e r d d a e c i v e d cs 010100a1a01011r1 r0p1p076543210 cs write data register (dr) a t a d n o i t c u r t s n i s e s s e r d d a e c i v e d cs 010100a1a01100r1r0p1p076543210 cs high voltage write cycle read (wip) status a t a d n o i t c u r t s n i s e s s e r d d a e c i v e d cs 010100a1a0010100 0 1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 w i p cs sck si r w inc/dec command issued voltage out t wrid
DP7401 ? nidec copal electronics corp. 11 doc. no. md-2012 rev. h characteristics subject to change without notice instruction format (continued) global transfer data register (dr) to wiper control register (wcr) device addresses instruction cs 010100a1a00001r1r0 0 0 cs global transfer wiper control register ( wcr) to data register (dr) device addresses instruction cs 010100a1a01000r1r0 0 0 cs high voltage write cycle transfer wiper control register (wcr) to data register (dr) device addresses instruction cs 010100a1a01110r1r0p1p0 cs high voltage write cycle transfer data register (dr) to wiper control register (wcr) device addresses instruction cs 010100a1a01101r1r0p1p0 cs increment (i)/decrement (d) wiper control register (wcr) a t a d n o i t c u r t s n i s e s s e r d d a e c i v e d cs 010100a1a00010 0 0 p1p0i/di/d . . . i/d i/d cs note: (1) any write or transfer to the non-volatile data registers is followed by a high voltage cycle after cs goes high.
DP7401 doc. no. md-2012 rev. h 12 ? nidec copal electronics corp. characteristics subject to change without notice package outlines soic 24-lead 300mils (w) (1)(2) notes: (1) all dimensions are in millimeters, angles in degrees. (2) complies with jedec standard mo-013. q e1 e a1 a2 e pin#1 identification b d c a top view w e i v d n e w e i v e d i s q 1 q 1 h h l symbol min nom max a2.35 2.65 a1 0.10 0.30 a2 2.05 2.55 b0.31 0.51 c0.20 0.33 d 15.20 15.40 e10.11 10.51 e1 7.34 7.60 e 1.27 bsc h0.25 0.75 l0.40 1.27 q 0 8 q 15 15
DP7401 ? nidec copal electronics corp. 13 h . v e r 2 1 0 2 - d m . o n . c o d characteristics subject to change without notice tssop 24-lead 4.4mm (y) (1)(2) notes: (1) all dimensions are in millimeters, angles in degrees. (2) complies with jedec standard mo-153. q 1 a 1 a2 d top view w e i v d n e w e i v e d i s e e1 e b l1 c l a symbol min nom max 0 2 . 1 a a1 0.05 0.15 a2 0.80 1.05 b0.19 0.30 c 0.09 0.20 d7.707.807.90 e 6.25 6.40 6.55 e1 4.30 4.40 4.50 e 0.65 bsc l1.00ref l1 0.50 0.60 0.70 q 10 8
DP7401 doc. no. md-2012 rev. h 14 ? nidec copal electronics corp. characteristics subject to change without notice example of ordering information notes: (1) all packages are rohs-compliant (lead-free, halogen-free). (2) the device used in the above example is a DP7401wi-00-t1 (soic, industrial temperature, 100k ? , tape & reel). ordering part number DP7401wi-25 DP7401wi-10 DP7401wi-50 DP7401wi-00 DP7401yi-25 DP7401yi-10 DP7401yi-50 DP7401yi-00 prefix device # suffix dp 7401 w i -00 - t1 company id package w: soic y: tssop temperature range i = industrial (-40oc to 85oc) product numbe r 7401 resistance 25: 2.5k ? 10: 10k ? 50: 50k ? 00: 100k ? tape & reel t: tape & reel 1: 1000/reel - soic 2: 2000/reel - tssop
revision history 2 1 0 2 - d m : o n t n e m u c o d h : n o i s i v e r 8 0 : e t a d e u s s i /25/08 nidec copal electronics corp. makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. nidec copal electronics corp. products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the nidec copal el ectronics corp. product could create a situation where personal injury or death may occur. nidec copal electronics corp. reserves the right to make changes to or discontinue any product or service described herein with out notice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . nidec copal electronics corp. advises customers to obtain the current version of the relevant product information before placin g orders. circuit diagrams illustrate typical semiconductor applications and may not be complete. nidec copal electronics corp. japan head office nishi-shinjuku, kimuraya bldg., 7-5-25 nishi-shinjuku, shinjuku-ku, tokyo 160-0023 phone: +81-3-3364-7055 fax: +81-3-3364-7098 www.nidec-copal-electronics.com date revision description 03/31/2004 f changed preliminary designation to final eliminated commercial temp range in all areas updated potentiometer characteristics notes updated pin descriptions (a0, a1 and wp ) updated notes for absolute max ratings 80 and potentiometer characteristics 10/16/2007 g added example of ordering information deleted bga package added md- to document number 08/25/08 h update functional diagram update potentiometer characteristics notes update d.c. operating characteristics table update pin capacitance table

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